00001 /* IO DEFINITIONS AND MACROS FOR THE MCS912DG256B 00002 09/19/03 00003 EMAC.inc 00004 Nathan Z. Gustavson ngustavson@emacinc.com 00005 Emac.inc 00006 */ 00007 00008 #define IO_BASE 0 00009 /*macros 00010 */ 00011 #define ienable() __asm("cli"); 00012 #define idisable() __asm("orcc #0x10") 00013 #define xenable() __asm("andcc #0xbf") 00014 #define xdisable()__asm("orcc #0x40") 00015 00016 00017 00018 /* Core HC12 Registers 00019 */ 00020 #define PORTA *(volatile unsigned char *)(IO_BASE + 0x00) /* port A */ 00021 #define PORTB *(volatile unsigned char *)(IO_BASE + 0x01) /* port B */ 00022 #define DDRA *(volatile unsigned char *)(IO_BASE + 0x02) /* data direction port A */ 00023 #define DDRB *(volatile unsigned char *)(IO_BASE + 0x03) /* data direction port B */ 00024 #define PORTE *(volatile unsigned char *)(IO_BASE + 0x08) /* port E */ 00025 #define DDRE *(volatile unsigned char *)(IO_BASE + 0x09) /* data direction port E */ 00026 #define PEAR *(volatile unsigned char *)(IO_BASE + 0x0a) /* port E assignment register */ 00027 #define MODE *(volatile unsigned char *)(IO_BASE + 0x0b) /* mode register */ 00028 #define PUCR *(volatile unsigned char *)(IO_BASE + 0x0c) /* pull-up control register */ 00029 #define RDRIV *(volatile unsigned char *)(IO_BASE + 0x0d) /* reduced drive of I/O lines */ 00030 #define EBICTL *(volatile unsigned char *)(IO_BASE + 0x0e) /* external bus control */ 00031 #define INITRM *(volatile unsigned char *)(IO_BASE + 0x10) /* RAM mapping register */ 00032 #define INITRG *(volatile unsigned char *)(IO_BASE + 0x11) /* IO mapping register */ 00033 #define INITEE *(volatile unsigned char *)(IO_BASE + 0x12) /* EEPROM mapping register */ 00034 #define MISC *(volatile unsigned char *)(IO_BASE + 0x13) /* mapping control register */ 00035 #define MTST0 *(volatile unsigned char *)(IO_BASE + 0x14) /* mapping test register 0 */ 00036 #define ITCR *(volatile unsigned char *)(IO_BASE + 0x15) /* interrupt test control reg. */ 00037 #define ITEST *(volatile unsigned char *)(IO_BASE + 0x16) /* interrupt test register */ 00038 #define MTST1 *(volatile unsigned char *)(IO_BASE + 0x17) /* mapping test register 1 */ 00039 #define PARTID *(volatile unsigned short int *)(IO_BASE + 0x1a) /* part ID register */ 00040 #define MEMSIZ0 *(volatile unsigned char *)(IO_BASE + 0x1c) /* memory size register 0 */ 00041 #define MEMSIZ1 *(volatile unsigned char *)(IO_BASE + 0x1d) /* memory size register 1 */ 00042 #define INTCR *(volatile unsigned char *)(IO_BASE + 0x1e) /* interrupt control */ 00043 #define HPRIO *(volatile unsigned char *)(IO_BASE + 0x1f) /* highest priority */ 00044 00045 /* 00046 bitflags 00047 */ 00048 //INTCR bitflags 00049 #define IRQE 0x80 00050 #define IRQEN 0x40 00051 #define DLY 0x20 00052 00053 /* BKP Module 00054 */ 00055 #define BKPCT0 *(volatile unsigned char *)(IO_BASE + 0x28) /* Breakpoint Control 0 */ 00056 #define BKPCT1 *(volatile unsigned char *)(IO_BASE + 0x29) /* Breakpoint Control 1 */ 00057 #define BKP0X *(volatile unsigned char *)(IO_BASE + 0x2a) /* Breakpoint 0 address upper */ 00058 #define BKP0 *(volatile unsigned short int *)(IO_BASE + 0x2b) /* Breakpoint 0 address */ 00059 #define BKP1X *(volatile unsigned char *)(IO_BASE + 0x2d) /* Breakpoint 1 address upper */ 00060 #define BKP1 *(volatile unsigned short int *)(IO_BASE + 0x2e) /* Breakpoint 1 address */ 00061 00062 /* MEBI Module 00063 */ 00064 #define PPAGE *(volatile unsigned char *)(IO_BASE + 0x30) /* program page register */ 00065 #define PORTK *(volatile unsigned char *)(IO_BASE + 0x32) /* port K data register */ 00066 #define DDRK *(volatile unsigned char *)(IO_BASE + 0x33) /* port K data direction */ 00067 00068 /* CRG Module 00069 */ 00070 #define SYNR *(volatile unsigned char *)(IO_BASE + 0x34) /* synthesizer register */ 00071 #define REFDV *(volatile unsigned char *)(IO_BASE + 0x35) /* reference divider register */ 00072 #define CTFLG *(volatile unsigned char *)(IO_BASE + 0x36) /* clock test flag register */ 00073 #define CRGFLG *(volatile unsigned char *)(IO_BASE + 0x37) /* clock generator flag register */ 00074 #define CRGINT *(volatile unsigned char *)(IO_BASE + 0x38) /* clock interrupt enable */ 00075 #define CLKSEL *(volatile unsigned char *)(IO_BASE + 0x39) /* clock select register */ 00076 #define PLLCTL *(volatile unsigned char *)(IO_BASE + 0x3a) /* PLL control register */ 00077 #define RTICTL *(volatile unsigned char *)(IO_BASE + 0x3b) /* clock real time control reg. */ 00078 #define COPCTL *(volatile unsigned char *)(IO_BASE + 0x3c) /* COP control register */ 00079 #define FORBYP *(volatile unsigned char *)(IO_BASE + 0x3d) /* clock force and bypass register */ 00080 #define CTCTL *(volatile unsigned char *)(IO_BASE + 0x3e) /* clock test control register */ 00081 #define ARMCOP *(volatile unsigned char *)(IO_BASE + 0x3f) /* COP arm/reset register */ 00082 00083 /* ECT Module 00084 */ 00085 #define TIOS *(volatile unsigned char *)(IO_BASE + 0x40) /* timer select register */ 00086 #define TCFORC *(volatile unsigned char *)(IO_BASE + 0x41) /* compare force register */ 00087 #define TOC7M *(volatile unsigned char *)(IO_BASE + 0x42) /* oc7 mask register */ 00088 #define TOC7D *(volatile unsigned char *)(IO_BASE + 0x43) /* oc7 data register */ 00089 #define TCNT *(volatile unsigned short int *)(IO_BASE + 0x44) /* timer counter */ 00090 #define TSCR1 *(volatile unsigned char *)(IO_BASE + 0x46) /* system control register 1 */ 00091 #define TTOV *(volatile unsigned char *)(IO_BASE + 0x47) /* toggle on overflow register */ 00092 #define TCTL1 *(volatile unsigned char *)(IO_BASE + 0x48) /* control register 1 */ 00093 #define TCTL2 *(volatile unsigned char *)(IO_BASE + 0x49) /* control register 2 */ 00094 #define TCTL3 *(volatile unsigned char *)(IO_BASE + 0x4a) /* control register 3 */ 00095 #define TCTL4 *(volatile unsigned char *)(IO_BASE + 0x4b) /* control register 4 */ 00096 #define TIE *(volatile unsigned char *)(IO_BASE + 0x4c) /* interrupt enable register */ 00097 #define TSCR2 *(volatile unsigned char *)(IO_BASE + 0x4d) /* system control register 2 */ 00098 #define TFLG1 *(volatile unsigned char *)(IO_BASE + 0x4e) /* interrupt flag register 1 */ 00099 #define TFLG2 *(volatile unsigned char *)(IO_BASE + 0x4f) /* interrupt flag register 2 */ 00100 #define TC0 *(volatile unsigned short int *)(IO_BASE + 0x50) /* capture/compare register 0 */ 00101 #define TC1 *(volatile unsigned short int *)(IO_BASE + 0x52) /* capture/compare register 0 */ 00102 #define TC2 *(volatile unsigned short int *)(IO_BASE + 0x54) /* capture/compare register 0 */ 00103 #define TC3 *(volatile unsigned short int *)(IO_BASE + 0x56) /* capture/compare register 0 */ 00104 #define TC4 *(volatile unsigned short int *)(IO_BASE + 0x58) /* capture/compare register 0 */ 00105 #define TC5 *(volatile unsigned short int *)(IO_BASE + 0x5a) /* capture/compare register 0 */ 00106 #define TC6 *(volatile unsigned short int *)(IO_BASE + 0x5c) /* capture/compare register 0 */ 00107 #define TC7 *(volatile unsigned short int *)(IO_BASE + 0x5e) /* capture/compare register 0 */ 00108 #define PACTL *(volatile unsigned char *)(IO_BASE + 0x60) /* pulse accumulator A control */ 00109 #define PAFLG *(volatile unsigned char *)(IO_BASE + 0x61) /* pulse accumulator A flag */ 00110 #define PACN3 *(volatile unsigned char *)(IO_BASE + 0x62) /* pulse accumulator A3 count */ 00111 #define PACN2 *(volatile unsigned char *)(IO_BASE + 0x63) /* pulse accumulator A2 count */ 00112 #define PACN1 *(volatile unsigned char *)(IO_BASE + 0x64) /* pulse accumulator A1 count */ 00113 #define PACN0 *(volatile unsigned char *)(IO_BASE + 0x65) /* pulse accumulator A0 count */ 00114 #define MCCTL *(volatile unsigned char *)(IO_BASE + 0x66) /* modulus counter control reg */ 00115 #define MCFLG *(volatile unsigned char *)(IO_BASE + 0x67) /* modulus counter flag reg */ 00116 #define ICPAR *(volatile unsigned char *)(IO_BASE + 0x68) /* input control pulse acc reg */ 00117 #define DLYCT *(volatile unsigned char *)(IO_BASE + 0x69) /* delay counter control reg */ 00118 #define ICOVW *(volatile unsigned char *)(IO_BASE + 0x6a) /* input control overwrite reg */ 00119 #define ICSYS *(volatile unsigned char *)(IO_BASE + 0x6b) /* input control system reg */ 00120 #define TIMTST *(volatile unsigned char *)(IO_BASE + 0x6d) /* timer test register */ 00121 #define PBCTL *(volatile unsigned char *)(IO_BASE + 0x70) /* pulse accumulator B control */ 00122 #define PBFLG *(volatile unsigned char *)(IO_BASE + 0x71) /* pulse accumulator B flag */ 00123 #define PA3H *(volatile unsigned char *)(IO_BASE + 0x72) /* pulse accumulator B3 count */ 00124 #define PA2H *(volatile unsigned char *)(IO_BASE + 0x73) /* pulse accumulator B2 count */ 00125 #define PA1H *(volatile unsigned char *)(IO_BASE + 0x74) /* pulse accumulator B1 count */ 00126 #define PA0H *(volatile unsigned char *)(IO_BASE + 0x75) /* pulse accumulator B0 count */ 00127 #define MCCNT *(volatile unsigned short int *)(IO_BASE + 0x76) /* modulus counter count reg */ 00128 #define TC0H *(volatile unsigned short int *)(IO_BASE + 0x78) /* timer input capture hold 0 */ 00129 #define TC1H *(volatile unsigned short int *)(IO_BASE + 0x7a) /* timer input capture hold 1 */ 00130 #define TC2H *(volatile unsigned short int *)(IO_BASE + 0x7c) /* timer input capture hold 2 */ 00131 #define TC3H *(volatile unsigned short int *)(IO_BASE + 0x7e) /* timer input capture hold 3 */ 00132 00133 /* ATD0 Module 00134 */ 00135 #define ATD0CTL0 *(volatile unsigned char *)(IO_BASE + 0x80) /* A/D0 control register 0 */ 00136 #define ATD0CTL1 *(volatile unsigned char *)(IO_BASE + 0x81) /* A/D0 control register 1 */ 00137 #define ATD0CTL2 *(volatile unsigned char *)(IO_BASE + 0x82) /* A/D0 control register 2 */ 00138 #define ATD0CTL3 *(volatile unsigned char *)(IO_BASE + 0x83) /* A/D0 control register 3 */ 00139 #define ATD0CTL4 *(volatile unsigned char *)(IO_BASE + 0x84) /* A/D0 control register 4 */ 00140 #define ATD0CTL5 *(volatile unsigned char *)(IO_BASE + 0x85) /* A/D0 control register 5 */ 00141 #define ATD0STAT0 *(volatile unsigned char *)(IO_BASE + 0x86) /* A/D0 status register 0 */ 00142 #define ATD0STAT1 *(volatile unsigned char *)(IO_BASE + 0x87) /* A/D0 status register 1 */ 00143 #define ATD0TEST0 *(volatile unsigned char *)(IO_BASE + 0x88) /* A/D0 test register 0 */ 00144 #define ATD0TEST1 *(volatile unsigned char *)(IO_BASE + 0x89) /* A/D0 test register 1 */ 00145 #define ATD0DIEN *(volatile unsigned char *)(IO_BASE + 0x8d) /* A/D0 interrupt enable */ 00146 #define PORTAD0 *(volatile unsigned char *)(IO_BASE + 0x8f) /* port AD0 data input register */ 00147 #define ATD0DR0 *(volatile unsigned short int *)(IO_BASE + 0x90) /* A/D0 result 0 */ 00148 #define ATD0DR1 *(volatile unsigned short int *)(IO_BASE + 0x92) /* A/D0 result 1 */ 00149 #define ATD0DR2 *(volatile unsigned short int *)(IO_BASE + 0x94) /* A/D0 result 2 */ 00150 #define ATD0DR3 *(volatile unsigned short int *)(IO_BASE + 0x96) /* A/D0 result 3 */ 00151 #define ATD0DR4 *(volatile unsigned short int *)(IO_BASE + 0x98) /* A/D0 result 4 */ 00152 #define ATD0DR5 *(volatile unsigned short int *)(IO_BASE + 0x9a) /* A/D0 result 5 */ 00153 #define ATD0DR6 *(volatile unsigned short int *)(IO_BASE + 0x9c) /* A/D0 result 6 */ 00154 #define ATD0DR7 *(volatile unsigned short int *)(IO_BASE + 0x9e) /* A/D0 result 7 */ 00155 00156 /* PWM Module 00157 */ 00158 #define PWME *(volatile unsigned char *)(IO_BASE + 0xa0) /* PWM Enable */ 00159 #define PWMPOL *(volatile unsigned char *)(IO_BASE + 0xa1) /* PWM Clock Polarity */ 00160 #define PWMCLK *(volatile unsigned char *)(IO_BASE + 0xa2) /* PWM Clocks */ 00161 #define PWMPRCLK *(volatile unsigned char *)(IO_BASE + 0xa3) /* PWM prescale clock select */ 00162 #define PWMCAE *(volatile unsigned char *)(IO_BASE + 0xa4) /* PWM center align enable */ 00163 #define PWMCTL *(volatile unsigned char *)(IO_BASE + 0xa5) /* PWM Control Register */ 00164 #define PWMTST *(volatile unsigned char *)(IO_BASE + 0xa6) /* PWM Test Register */ 00165 #define PWMPRSC *(volatile unsigned char *)(IO_BASE + 0xa7) /* PWM Test Register */ 00166 #define PWMSCLA *(volatile unsigned char *)(IO_BASE + 0xa8) /* PWM scale A */ 00167 #define PWMSCLB *(volatile unsigned char *)(IO_BASE + 0xa9) /* PWM scale B */ 00168 #define PWMSCNTA *(volatile unsigned char *)(IO_BASE + 0xaa) /* PWM Test Register A */ 00169 #define PWMSCNTB *(volatile unsigned char *)(IO_BASE + 0xab) /* PWM Test Register B */ 00170 #define PWMCNT0 *(volatile unsigned char *)(IO_BASE + 0xac) /* PWM Channel Counter 0 */ 00171 #define PWMCNT1 *(volatile unsigned char *)(IO_BASE + 0xad) /* PWM Channel Counter 1 */ 00172 #define PWMCNT2 *(volatile unsigned char *)(IO_BASE + 0xae) /* PWM Channel Counter 2 */ 00173 #define PWMCNT3 *(volatile unsigned char *)(IO_BASE + 0xaf) /* PWM Channel Counter 3 */ 00174 #define PWMCNT4 *(volatile unsigned char *)(IO_BASE + 0xb0) /* PWM Channel Counter 4 */ 00175 #define PWMCNT5 *(volatile unsigned char *)(IO_BASE + 0xb1) /* PWM Channel Counter 5 */ 00176 #define PWMCNT6 *(volatile unsigned char *)(IO_BASE + 0xb2) /* PWM Channel Counter 6 */ 00177 #define PWMCNT7 *(volatile unsigned char *)(IO_BASE + 0xb3) /* PWM Channel Counter 7 */ 00178 #define PWMPER0 *(volatile unsigned char *)(IO_BASE + 0xb4) /* PWM Channel Period 0 */ 00179 #define PWMPER1 *(volatile unsigned char *)(IO_BASE + 0xb5) /* PWM Channel Period 1 */ 00180 #define PWMPER2 *(volatile unsigned char *)(IO_BASE + 0xb6) /* PWM Channel Period 2 */ 00181 #define PWMPER3 *(volatile unsigned char *)(IO_BASE + 0xb7) /* PWM Channel Period 3 */ 00182 #define PWMPER4 *(volatile unsigned char *)(IO_BASE + 0xb8) /* PWM Channel Period 4 */ 00183 #define PWMPER5 *(volatile unsigned char *)(IO_BASE + 0xb9) /* PWM Channel Period 5 */ 00184 #define PWMPER6 *(volatile unsigned char *)(IO_BASE + 0xba) /* PWM Channel Period 6 */ 00185 #define PWMPER7 *(volatile unsigned char *)(IO_BASE + 0xbb) /* PWM Channel Period 7 */ 00186 #define PWMDTY0 *(volatile unsigned char *)(IO_BASE + 0xbc) /* PWM Channel Duty 0 */ 00187 #define PWMDTY1 *(volatile unsigned char *)(IO_BASE + 0xbd) /* PWM Channel Duty 1 */ 00188 #define PWMDTY2 *(volatile unsigned char *)(IO_BASE + 0xbe) /* PWM Channel Duty 2 */ 00189 #define PWMDTY3 *(volatile unsigned char *)(IO_BASE + 0xbf) /* PWM Channel Duty 3 */ 00190 #define PWMDTY4 *(volatile unsigned char *)(IO_BASE + 0xc0) /* PWM Channel Duty 4 */ 00191 #define PWMDTY5 *(volatile unsigned char *)(IO_BASE + 0xc1) /* PWM Channel Duty 5 */ 00192 #define PWMDTY6 *(volatile unsigned char *)(IO_BASE + 0xc2) /* PWM Channel Duty 6 */ 00193 #define PWMDTY7 *(volatile unsigned char *)(IO_BASE + 0xc3) /* PWM Channel Duty 7 */ 00194 #define PWMSDN *(volatile unsigned char *)(IO_BASE + 0xc4) /* PWM shutdown register */ 00195 00196 /* SCI0 Module 00197 */ 00198 #define SCI0BDH *(volatile unsigned char *)(IO_BASE + 0xc8) /* SCI 0 baud rate high */ 00199 #define SCI0BDL *(volatile unsigned char *)(IO_BASE + 0xc9) /* SCI 0 baud rate low */ 00200 #define SCI0CR1 *(volatile unsigned char *)(IO_BASE + 0xca) /* SCI 0 control register 1 */ 00201 #define SCI0CR2 *(volatile unsigned char *)(IO_BASE + 0xcb) /* SCI 0 control register 2 */ 00202 #define SCI0SR1 *(volatile unsigned char *)(IO_BASE + 0xcc) /* SCI 0 status register 1 */ 00203 #define SCI0SR2 *(volatile unsigned char *)(IO_BASE + 0xcd) /* SCI 0 status register 2 */ 00204 #define SCI0DRH *(volatile unsigned char *)(IO_BASE + 0xce) /* SCI 0 data register high */ 00205 #define SCI0DRL *(volatile unsigned char *)(IO_BASE + 0xcf) /* SCI 0 data register low */ 00206 00207 /* SCI1 Module 00208 */ 00209 #define SCI1BDH *(volatile unsigned char *)(IO_BASE + 0xd0) /* SCI 1 baud rate high */ 00210 #define SCI1BDL *(volatile unsigned char *)(IO_BASE + 0xd1) /* SCI 1 baud rate low */ 00211 #define SCI1CR1 *(volatile unsigned char *)(IO_BASE + 0xd2) /* SCI 1 control register 1 */ 00212 #define SCI1CR2 *(volatile unsigned char *)(IO_BASE + 0xd3) /* SCI 1 control register 2 */ 00213 #define SCI1SR1 *(volatile unsigned char *)(IO_BASE + 0xd4) /* SCI 1 status register 1 */ 00214 #define SCI1SR2 *(volatile unsigned char *)(IO_BASE + 0xd5) /* SCI 1 status register 2 */ 00215 #define SCI1DRH *(volatile unsigned char *)(IO_BASE + 0xd6) /* SCI 1 data register high */ 00216 #define SCI1DRL *(volatile unsigned char *)(IO_BASE + 0xd7) /* SCI 1 data register low */ 00217 00218 /* SPI0 Module 00219 */ 00220 #define SPI0CR1 *(volatile unsigned char *)(IO_BASE + 0xd8) /* SPI 0 control register 1 */ 00221 #define SPI0CR2 *(volatile unsigned char *)(IO_BASE + 0xd9) /* SPI 0 control register 2 */ 00222 #define SPI0BR *(volatile unsigned char *)(IO_BASE + 0xda) /* SPI 0 baud rate register */ 00223 #define SPI0SR *(volatile unsigned char *)(IO_BASE + 0xdb) /* SPI 0 status register */ 00224 #define SPI0DR *(volatile unsigned char *)(IO_BASE + 0xdd) /* SPI 0 data register */ 00225 00226 /* I2C Module 00227 */ 00228 #define IBAD *(volatile unsigned char *)(IO_BASE + 0xe0) /* I2C address register */ 00229 #define IBFD *(volatile unsigned char *)(IO_BASE + 0xe1) /* I2C freqency divider reg */ 00230 #define IBCR *(volatile unsigned char *)(IO_BASE + 0xe2) /* I2C control register */ 00231 #define IBSR *(volatile unsigned char *)(IO_BASE + 0xe3) /* I2C status register */ 00232 #define IBDR *(volatile unsigned char *)(IO_BASE + 0xe4) /* I2C data register */ 00233 00234 /* BDLC Module 00235 */ 00236 #define DLCBCR1 *(volatile unsigned char *)(IO_BASE + 0xe8) /* BDLC control register 1 */ 00237 #define DLCBSVR *(volatile unsigned char *)(IO_BASE + 0xe9) /* BDLC state vector register */ 00238 #define DLCBCR2 *(volatile unsigned char *)(IO_BASE + 0xea) /* BDLC control register 2 */ 00239 #define DLCBDR *(volatile unsigned char *)(IO_BASE + 0xeb) /* BDLC data register */ 00240 #define DLCBARD *(volatile unsigned char *)(IO_BASE + 0xec) /* BDLC analog round trip delay */ 00241 #define DLCBRSR *(volatile unsigned char *)(IO_BASE + 0xed) /* BDLC rate select register */ 00242 #define DLCSCR *(volatile unsigned char *)(IO_BASE + 0xee) /* BDLC control register */ 00243 #define DLCBSTAT *(volatile unsigned char *)(IO_BASE + 0xef) /* BDLC status register */ 00244 00245 /* SPI1 Module 00246 */ 00247 #define SPI1CR1 *(volatile unsigned char *)(IO_BASE + 0xf0) /* SPI 1 control register 1 */ 00248 #define SPI1CR2 *(volatile unsigned char *)(IO_BASE + 0xf1) /* SPI 1 control register 2 */ 00249 #define SPI1BR *(volatile unsigned char *)(IO_BASE + 0xf2) /* SPI 1 baud rate register */ 00250 #define SPI1SR *(volatile unsigned char *)(IO_BASE + 0xf3) /* SPI 1 status register */ 00251 #define SPI1DR *(volatile unsigned char *)(IO_BASE + 0xf5) /* SPI 1 data register */ 00252 00253 /* SPI2 Module 00254 */ 00255 #define SPI2CR1 *(volatile unsigned char *)(IO_BASE + 0xf8) /* SPI 2 control register 1 */ 00256 #define SPI2CR2 *(volatile unsigned char *)(IO_BASE + 0xf9) /* SPI 2 control register 2 */ 00257 #define SPI2BR *(volatile unsigned char *)(IO_BASE + 0xfa) /* SPI 2 baud rate register */ 00258 #define SPI2SR *(volatile unsigned char *)(IO_BASE + 0xfb) /* SPI 2 status register */ 00259 #define SPI2DR *(volatile unsigned char *)(IO_BASE + 0xfd) /* SPI 2 data register */ 00260 00261 /* FLC Module 00262 */ 00263 #define FCLKDIV *(volatile unsigned char *)(IO_BASE + 0x100) /* flash clock divider */ 00264 #define FSEC *(volatile unsigned char *)(IO_BASE + 0x101) /* flash security register */ 00265 #define FCNFG *(volatile unsigned char *)(IO_BASE + 0x103) /* flash configuration register */ 00266 #define FPROT *(volatile unsigned char *)(IO_BASE + 0x104) /* flash protection register */ 00267 #define FSTAT *(volatile unsigned char *)(IO_BASE + 0x105) /* flash status register */ 00268 #define FCMD *(volatile unsigned char *)(IO_BASE + 0x106) /* flash command register */ 00269 00270 /* EEPROM Module 00271 */ 00272 #define ECLKDIV *(volatile unsigned char *)(IO_BASE + 0x110) /* eeprom clock divider */ 00273 #define ECNFG *(volatile unsigned char *)(IO_BASE + 0x113) /* eeprom configuration register */ 00274 #define EPROT *(volatile unsigned char *)(IO_BASE + 0x114) /* eeprom protection register */ 00275 #define ESTAT *(volatile unsigned char *)(IO_BASE + 0x115) /* eeprom status register */ 00276 #define ECMD *(volatile unsigned char *)(IO_BASE + 0x116) /* eeprom command register */ 00277 00278 /* ATD1 Module 00279 */ 00280 #define ATD1CTL0 *(volatile unsigned char *)(IO_BASE + 0x120) /* A/D1 control register 0 */ 00281 #define ATD1CTL1 *(volatile unsigned char *)(IO_BASE + 0x121) /* A/D1 control register 1 */ 00282 #define ATD1CTL2 *(volatile unsigned char *)(IO_BASE + 0x122) /* A/D1 control register 2 */ 00283 #define ATD1CTL3 *(volatile unsigned char *)(IO_BASE + 0x123) /* A/D1 control register 3 */ 00284 #define ATD1CTL4 *(volatile unsigned char *)(IO_BASE + 0x124) /* A/D1 control register 4 */ 00285 #define ATD1CTL5 *(volatile unsigned char *)(IO_BASE + 0x125) /* A/D1 control register 5 */ 00286 #define ATD1STAT0 *(volatile unsigned char *)(IO_BASE + 0x126) /* A/D1 status register 0 */ 00287 #define ATD1STAT1 *(volatile unsigned char *)(IO_BASE + 0x127) /* A/D1 status register 1 */ 00288 #define ATD1TEST0 *(volatile unsigned char *)(IO_BASE + 0x128) /* A/D1 test register 0 */ 00289 #define ATD1TEST1 *(volatile unsigned char *)(IO_BASE + 0x129) /* A/D1 test register 1 */ 00290 #define ATD1DIEN *(volatile unsigned char *)(IO_BASE + 0x12d) /* A/D1 interrupt enable */ 00291 #define PORTAD1 *(volatile unsigned char *)(IO_BASE + 0x12f) /* port AD1 data input register */ 00292 #define ATD1DR0 *(volatile unsigned short int *)(IO_BASE + 0x130) /* A/D1 result 0 */ 00293 #define ATD1DR1 *(volatile unsigned short int *)(IO_BASE + 0x132) /* A/D1 result 1 */ 00294 #define ATD1DR2 *(volatile unsigned short int *)(IO_BASE + 0x134) /* A/D1 result 2 */ 00295 #define ATD1DR3 *(volatile unsigned short int *)(IO_BASE + 0x136) /* A/D1 result 3 */ 00296 #define ATD1DR4 *(volatile unsigned short int *)(IO_BASE + 0x138) /* A/D1 result 4 */ 00297 #define ATD1DR5 *(volatile unsigned short int *)(IO_BASE + 0x13a) /* A/D1 result 5 */ 00298 #define ATD1DR6 *(volatile unsigned short int *)(IO_BASE + 0x13c) /* A/D1 result 6 */ 00299 #define ATD1DR7 *(volatile unsigned short int *)(IO_BASE + 0x13e) /* A/D1 result 7 */ 00300 00301 /* CAN0 Module 00302 */ 00303 #define CAN0CTL0 *(volatile unsigned char *)(IO_BASE + 0x140) /* CAN0 control register 0 */ 00304 #define CAN0CTL1 *(volatile unsigned char *)(IO_BASE + 0x141) /* CAN0 control register 1 */ 00305 #define CAN0BTR0 *(volatile unsigned char *)(IO_BASE + 0x142) /* CAN0 bus timing register 0 */ 00306 #define CAN0BTR1 *(volatile unsigned char *)(IO_BASE + 0x143) /* CAN0 bus timing register 1 */ 00307 #define CAN0RFLG *(volatile unsigned char *)(IO_BASE + 0x144) /* CAN0 receiver flag register */ 00308 #define CAN0RIER *(volatile unsigned char *)(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */ 00309 #define CAN0TFLG *(volatile unsigned char *)(IO_BASE + 0x146) /* CAN0 transmitter flag reg */ 00310 #define CAN0TIER *(volatile unsigned char *)(IO_BASE + 0x147) /* CAN0 transmitter control reg */ 00311 #define CAN0TARQ *(volatile unsigned char *)(IO_BASE + 0x148) /* CAN0 transmitter abort request */ 00312 #define CAN0TAAK *(volatile unsigned char *)(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */ 00313 #define CAN0TBSEL *(volatile unsigned char *)(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */ 00314 #define CAN0IDAC *(volatile unsigned char *)(IO_BASE + 0x14b) /* CAN0 identifier acceptance */ 00315 #define CAN0RXERR *(volatile unsigned char *)(IO_BASE + 0x14e) /* CAN0 receive error counter */ 00316 #define CAN0TXERR *(volatile unsigned char *)(IO_BASE + 0x14f) /* CAN0 transmit error counter */ 00317 #define CAN0IDAR0 *(volatile unsigned char *)(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */ 00318 #define CAN0IDAR1 *(volatile unsigned char *)(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */ 00319 #define CAN0IDAR2 *(volatile unsigned char *)(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */ 00320 #define CAN0IDAR3 *(volatile unsigned char *)(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */ 00321 #define CAN0IDMR0 *(volatile unsigned char *)(IO_BASE + 0x154) /* CAN0 id mask register 0 */ 00322 #define CAN0IDMR1 *(volatile unsigned char *)(IO_BASE + 0x155) /* CAN0 id mask register 1 */ 00323 #define CAN0IDMR2 *(volatile unsigned char *)(IO_BASE + 0x156) /* CAN0 id mask register 2 */ 00324 #define CAN0IDMR3 *(volatile unsigned char *)(IO_BASE + 0x157) /* CAN0 id mask register 3 */ 00325 #define CAN0IDAR4 *(volatile unsigned char *)(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */ 00326 #define CAN0IDAR5 *(volatile unsigned char *)(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */ 00327 #define CAN0IDAR6 *(volatile unsigned char *)(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */ 00328 #define CAN0IDAR7 *(volatile unsigned char *)(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */ 00329 #define CAN0IDMR4 *(volatile unsigned char *)(IO_BASE + 0x15c) /* CAN0 id mask register 4 */ 00330 #define CAN0IDMR5 *(volatile unsigned char *)(IO_BASE + 0x15d) /* CAN0 id mask register 5 */ 00331 #define CAN0IDMR6 *(volatile unsigned char *)(IO_BASE + 0x15e) /* CAN0 id mask register 6 */ 00332 #define CAN0IDMR7 *(volatile unsigned char *)(IO_BASE + 0x15f) /* CAN0 id mask register 7 */ 00333 #define CAN0RXFG *(volatile unsigned char *)(IO_BASE + 0x160) /* CAN0 receive buffer */ 00334 #define CAN0TXFG *(volatile unsigned char *)(IO_BASE + 0x170) /* CAN0 transmit buffer */ 00335 00336 /* CAN1 Module 00337 */ 00338 #define CAN1CTL0 *(volatile unsigned char *)(IO_BASE + 0x180) /* CAN1 control register 0 */ 00339 #define CAN1CTL1 *(volatile unsigned char *)(IO_BASE + 0x181) /* CAN1 control register 1 */ 00340 #define CAN1BTR0 *(volatile unsigned char *)(IO_BASE + 0x182) /* CAN1 bus timing register 0 */ 00341 #define CAN1BTR1 *(volatile unsigned char *)(IO_BASE + 0x183) /* CAN1 bus timing register 1 */ 00342 #define CAN1RFLG *(volatile unsigned char *)(IO_BASE + 0x184) /* CAN1 receiver flag register */ 00343 #define CAN1RIER *(volatile unsigned char *)(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */ 00344 #define CAN1TFLG *(volatile unsigned char *)(IO_BASE + 0x186) /* CAN1 transmitter flag reg */ 00345 #define CAN1TIER *(volatile unsigned char *)(IO_BASE + 0x187) /* CAN1 transmitter control reg */ 00346 #define CAN1TARQ *(volatile unsigned char *)(IO_BASE + 0x188) /* CAN1 transmitter abort request */ 00347 #define CAN1TAAK *(volatile unsigned char *)(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */ 00348 #define CAN1TBSEL *(volatile unsigned char *)(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */ 00349 #define CAN1IDAC *(volatile unsigned char *)(IO_BASE + 0x18b) /* CAN1 identifier acceptance */ 00350 #define CAN1RXERR *(volatile unsigned char *)(IO_BASE + 0x18e) /* CAN1 transmitter control reg */ 00351 #define CAN1TXERR *(volatile unsigned char *)(IO_BASE + 0x18f) /* CAN1 transmit error counter */ 00352 #define CAN1IDAR0 *(volatile unsigned char *)(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */ 00353 #define CAN1IDAR1 *(volatile unsigned char *)(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */ 00354 #define CAN1IDAR2 *(volatile unsigned char *)(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */ 00355 #define CAN1IDAR3 *(volatile unsigned char *)(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */ 00356 #define CAN1IDMR0 *(volatile unsigned char *)(IO_BASE + 0x194) /* CAN1 id mask register 0 */ 00357 #define CAN1IDMR1 *(volatile unsigned char *)(IO_BASE + 0x195) /* CAN1 id mask register 1 */ 00358 #define CAN1IDMR2 *(volatile unsigned char *)(IO_BASE + 0x196) /* CAN1 id mask register 2 */ 00359 #define CAN1IDMR3 *(volatile unsigned char *)(IO_BASE + 0x197) /* CAN1 id mask register 3 */ 00360 #define CAN1IDAR4 *(volatile unsigned char *)(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */ 00361 #define CAN1IDAR5 *(volatile unsigned char *)(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */ 00362 #define CAN1IDAR6 *(volatile unsigned char *)(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */ 00363 #define CAN1IDAR7 *(volatile unsigned char *)(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */ 00364 #define CAN1IDMR4 *(volatile unsigned char *)(IO_BASE + 0x19c) /* CAN1 id mask register 4 */ 00365 #define CAN1IDMR5 *(volatile unsigned char *)(IO_BASE + 0x19d) /* CAN1 id mask register 5 */ 00366 #define CAN1IDMR6 *(volatile unsigned char *)(IO_BASE + 0x19e) /* CAN1 id mask register 6 */ 00367 #define CAN1IDMR7 *(volatile unsigned char *)(IO_BASE + 0x19f) /* CAN1 id mask register 7 */ 00368 #define CAN1RXFG *(volatile unsigned char *)(IO_BASE + 0x1a0) /* CAN1 receive buffer */ 00369 #define CAN1TXFG *(volatile unsigned char *)(IO_BASE + 0x1b0) /* CAN1 transmit buffer */ 00370 00371 /* CAN2 Module 00372 */ 00373 #define CAN2CTL0 *(volatile unsigned char *)(IO_BASE + 0x1c0) /* CAN2 control register 0 */ 00374 #define CAN2CTL1 *(volatile unsigned char *)(IO_BASE + 0x1c1) /* CAN2 control register 1 */ 00375 #define CAN2BTR0 *(volatile unsigned char *)(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */ 00376 #define CAN2BTR1 *(volatile unsigned char *)(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */ 00377 #define CAN2RFLG *(volatile unsigned char *)(IO_BASE + 0x1c4) /* CAN2 receiver flag register */ 00378 #define CAN2RIER *(volatile unsigned char *)(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */ 00379 #define CAN2TFLG *(volatile unsigned char *)(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */ 00380 #define CAN2TIER *(volatile unsigned char *)(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */ 00381 #define CAN2TARQ *(volatile unsigned char *)(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */ 00382 #define CAN2TAAK *(volatile unsigned char *)(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */ 00383 #define CAN2TBSEL *(volatile unsigned char *)(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */ 00384 #define CAN2IDAC *(volatile unsigned char *)(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */ 00385 #define CAN2RXERR *(volatile unsigned char *)(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */ 00386 #define CAN2TXERR *(volatile unsigned char *)(IO_BASE + 0x1cf) /* CAN2 transmit error counter */ 00387 #define CAN2IDAR0 *(volatile unsigned char *)(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */ 00388 #define CAN2IDAR1 *(volatile unsigned char *)(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */ 00389 #define CAN2IDAR2 *(volatile unsigned char *)(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */ 00390 #define CAN2IDAR3 *(volatile unsigned char *)(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */ 00391 #define CAN2IDMR0 *(volatile unsigned char *)(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */ 00392 #define CAN2IDMR1 *(volatile unsigned char *)(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */ 00393 #define CAN2IDMR2 *(volatile unsigned char *)(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */ 00394 #define CAN2IDMR3 *(volatile unsigned char *)(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */ 00395 #define CAN2IDAR4 *(volatile unsigned char *)(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */ 00396 #define CAN2IDAR5 *(volatile unsigned char *)(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */ 00397 #define CAN2IDAR6 *(volatile unsigned char *)(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */ 00398 #define CAN2IDAR7 *(volatile unsigned char *)(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */ 00399 #define CAN2IDMR4 *(volatile unsigned char *)(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */ 00400 #define CAN2IDMR5 *(volatile unsigned char *)(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */ 00401 #define CAN2IDMR6 *(volatile unsigned char *)(IO_BASE + 0x1de) /* CAN2 id mask register 6 */ 00402 #define CAN2IDMR7 *(volatile unsigned char *)(IO_BASE + 0x1df) /* CAN2 id mask register 7 */ 00403 #define CAN2RXFG *(volatile unsigned char *)(IO_BASE + 0x1e0) /* CAN2 receive buffer */ 00404 #define CAN2TXFG *(volatile unsigned char *)(IO_BASE + 0x1f0) /* CAN2 transmit buffer */ 00405 00406 /* CAN3 Module 00407 */ 00408 #define CAN3CTL0 *(volatile unsigned char *)(IO_BASE + 0x200) /* CAN3 control register 0 */ 00409 #define CAN3CTL1 *(volatile unsigned char *)(IO_BASE + 0x201) /* CAN3 control register 1 */ 00410 #define CAN3BTR0 *(volatile unsigned char *)(IO_BASE + 0x202) /* CAN3 bus timing register 0 */ 00411 #define CAN3BTR1 *(volatile unsigned char *)(IO_BASE + 0x203) /* CAN3 bus timing register 1 */ 00412 #define CAN3RFLG *(volatile unsigned char *)(IO_BASE + 0x204) /* CAN3 receiver flag register */ 00413 #define CAN3RIER *(volatile unsigned char *)(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */ 00414 #define CAN3TFLG *(volatile unsigned char *)(IO_BASE + 0x206) /* CAN3 transmitter flag reg */ 00415 #define CAN3TIER *(volatile unsigned char *)(IO_BASE + 0x207) /* CAN3 transmitter control reg */ 00416 #define CAN3TARQ *(volatile unsigned char *)(IO_BASE + 0x208) /* CAN3 transmitter abort request */ 00417 #define CAN3TAAK *(volatile unsigned char *)(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */ 00418 #define CAN3TBSEL *(volatile unsigned char *)(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */ 00419 #define CAN3IDAC *(volatile unsigned char *)(IO_BASE + 0x20b) /* CAN3 identifier acceptance */ 00420 #define CAN3RXERR *(volatile unsigned char *)(IO_BASE + 0x20e) /* CAN3 transmitter control reg */ 00421 #define CAN3TXERR *(volatile unsigned char *)(IO_BASE + 0x20f) /* CAN3 transmit error counter */ 00422 #define CAN3IDAR0 *(volatile unsigned char *)(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */ 00423 #define CAN3IDAR1 *(volatile unsigned char *)(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */ 00424 #define CAN3IDAR2 *(volatile unsigned char *)(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */ 00425 #define CAN3IDAR3 *(volatile unsigned char *)(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */ 00426 #define CAN3IDMR0 *(volatile unsigned char *)(IO_BASE + 0x214) /* CAN3 id mask register 0 */ 00427 #define CAN3IDMR1 *(volatile unsigned char *)(IO_BASE + 0x215) /* CAN3 id mask register 1 */ 00428 #define CAN3IDMR2 *(volatile unsigned char *)(IO_BASE + 0x216) /* CAN3 id mask register 2 */ 00429 #define CAN3IDMR3 *(volatile unsigned char *)(IO_BASE + 0x217) /* CAN3 id mask register 3 */ 00430 #define CAN3IDAR4 *(volatile unsigned char *)(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */ 00431 #define CAN3IDAR5 *(volatile unsigned char *)(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */ 00432 #define CAN3IDAR6 *(volatile unsigned char *)(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */ 00433 #define CAN3IDAR7 *(volatile unsigned char *)(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */ 00434 #define CAN3IDMR4 *(volatile unsigned char *)(IO_BASE + 0x21c) /* CAN3 id mask register 4 */ 00435 #define CAN3IDMR5 *(volatile unsigned char *)(IO_BASE + 0x21d) /* CAN3 id mask register 5 */ 00436 #define CAN3IDMR6 *(volatile unsigned char *)(IO_BASE + 0x21e) /* CAN3 id mask register 6 */ 00437 #define CAN3IDMR7 *(volatile unsigned char *)(IO_BASE + 0x21f) /* CAN3 id mask register 7 */ 00438 #define CAN3RXFG *(volatile unsigned char *)(IO_BASE + 0x220) /* CAN3 receive buffer */ 00439 #define CAN3TXFG *(volatile unsigned char *)(IO_BASE + 0x230) /* CAN3 transmit buffer */ 00440 00441 /* PIM 00442 */ 00443 00444 /*Port T 00445 */ 00446 #define PTT *(volatile unsigned char *)(IO_BASE + 0x240) /* port T data register */ 00447 #define PTIT *(volatile unsigned char *)(IO_BASE + 0x241) /* port T input register */ 00448 #define DDRT *(volatile unsigned char *)(IO_BASE + 0x242) /* port T data direction */ 00449 #define RDRT *(volatile unsigned char *)(IO_BASE + 0x243) /* port T reduce drive */ 00450 #define PERT *(volatile unsigned char *)(IO_BASE + 0x244) /* port T pull enable */ 00451 #define PPST *(volatile unsigned char *)(IO_BASE + 0x245) /* port T polarity select */ 00452 00453 /*Port S 00454 */ 00455 #define PTS *(volatile unsigned char *)(IO_BASE + 0x248) /* port S data register */ 00456 #define PTIS *(volatile unsigned char *)(IO_BASE + 0x249) /* port S input register */ 00457 #define DDRS *(volatile unsigned char *)(IO_BASE + 0x24a) /* port S data direction */ 00458 #define RDRS *(volatile unsigned char *)(IO_BASE + 0x24b) /* port S reduce drive */ 00459 #define PERS *(volatile unsigned char *)(IO_BASE + 0x24c) /* port S pull enable */ 00460 #define PPSS *(volatile unsigned char *)(IO_BASE + 0x24d) /* port S polarity select */ 00461 #define WOMS *(volatile unsigned char *)(IO_BASE + 0x24e) /* port S wired-or mode */ 00462 00463 /* Port M 00464 */ 00465 #define PTM *(volatile unsigned char *)(IO_BASE + 0x250) /* port M data register */ 00466 #define PTIM *(volatile unsigned char *)(IO_BASE + 0x251) /* port M input register */ 00467 #define DDRM *(volatile unsigned char *)(IO_BASE + 0x252) /* port M data direction */ 00468 #define RDRM *(volatile unsigned char *)(IO_BASE + 0x253) /* port M reduce drive */ 00469 #define PERM *(volatile unsigned char *)(IO_BASE + 0x254) /* port M pull enable */ 00470 #define PPSM *(volatile unsigned char *)(IO_BASE + 0x255) /* port M polarity select */ 00471 #define WOMM *(volatile unsigned char *)(IO_BASE + 0x256) /* port M wired-or mode */ 00472 00473 /* Port P 00474 */ 00475 #define PTP *(volatile unsigned char *)(IO_BASE + 0x258) /* port P data register */ 00476 #define PTIP *(volatile unsigned char *)(IO_BASE + 0x259) /* port P input register */ 00477 #define DDRP *(volatile unsigned char *)(IO_BASE + 0x25a) /* port P data direction */ 00478 #define RDRP *(volatile unsigned char *)(IO_BASE + 0x25b) /* port P reduce drive */ 00479 #define PERP *(volatile unsigned char *)(IO_BASE + 0x25c) /* port P pull enable */ 00480 #define PPSP *(volatile unsigned char *)(IO_BASE + 0x25d) /* port P polarity select */ 00481 #define PIEP *(volatile unsigned char *)(IO_BASE + 0x25e) /* port P interrupt enable */ 00482 #define PIFP *(volatile unsigned char *)(IO_BASE + 0x25f) /* port P interrupt flag */ 00483 00484 /* Port H 00485 */ 00486 #define PTH *(volatile unsigned char *)(IO_BASE + 0x260) /* port H data register */ 00487 #define PTIH *(volatile unsigned char *)(IO_BASE + 0x261) /* port H input register */ 00488 #define DDRH *(volatile unsigned char *)(IO_BASE + 0x262) /* port H data direction */ 00489 #define RDRH *(volatile unsigned char *)(IO_BASE + 0x263) /* port H reduce drive */ 00490 #define PERH *(volatile unsigned char *)(IO_BASE + 0x264) /* port H pull enable */ 00491 #define PPSH *(volatile unsigned char *)(IO_BASE + 0x265) /* port H polarity select */ 00492 #define PIEH *(volatile unsigned char *)(IO_BASE + 0x266) /* port H interrupt enable */ 00493 #define PIFH *(volatile unsigned char *)(IO_BASE + 0x267) /* port H interrupt flag */ 00494 00495 /* Port J 00496 */ 00497 #define PTJ *(volatile unsigned char *)(IO_BASE + 0x268) /* port J data register */ 00498 #define PTIJ *(volatile unsigned char *)(IO_BASE + 0x269) /* port J input register */ 00499 #define DDRJ *(volatile unsigned char *)(IO_BASE + 0x26a) /* port J data direction */ 00500 #define RDRJ *(volatile unsigned char *)(IO_BASE + 0x26b) /* port J reduce drive */ 00501 #define PERJ *(volatile unsigned char *)(IO_BASE + 0x26c) /* port J pull enable */ 00502 #define PPSJ *(volatile unsigned char *)(IO_BASE + 0x26d) /* port J polarity select */ 00503 #define PIEJ *(volatile unsigned char *)(IO_BASE + 0x26e) /* port J interrupt enable */ 00504 #define PIFJ *(volatile unsigned char *)(IO_BASE + 0x26f) /* port J interrupt flag */ 00505 /*PIM end 00506 */ 00507 00508 00509 /* CAN4 Module 00510 */ 00511 #define CAN4CTL0 *(volatile unsigned char *)(IO_BASE + 0x280) /* CAN4 control register 0 */ 00512 #define CAN4CTL1 *(volatile unsigned char *)(IO_BASE + 0x281) /* CAN4 control register 1 */ 00513 #define CAN4BTR0 *(volatile unsigned char *)(IO_BASE + 0x282) /* CAN4 bus timing register 0 */ 00514 #define CAN4BTR1 *(volatile unsigned char *)(IO_BASE + 0x283) /* CAN4 bus timing register 1 */ 00515 #define CAN4RFLG *(volatile unsigned char *)(IO_BASE + 0x284) /* CAN4 receiver flag register */ 00516 #define CAN4RIER *(volatile unsigned char *)(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */ 00517 #define CAN4TFLG *(volatile unsigned char *)(IO_BASE + 0x286) /* CAN4 transmitter flag reg */ 00518 #define CAN4TIER *(volatile unsigned char *)(IO_BASE + 0x287) /* CAN4 transmitter control reg */ 00519 #define CAN4TARQ *(volatile unsigned char *)(IO_BASE + 0x288) /* CAN4 transmitter abort request */ 00520 #define CAN4TAAK *(volatile unsigned char *)(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */ 00521 #define CAN4TBSEL *(volatile unsigned char *)(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */ 00522 #define CAN4IDAC *(volatile unsigned char *)(IO_BASE + 0x28b) /* CAN4 identifier acceptance */ 00523 #define CAN4RXERR *(volatile unsigned char *)(IO_BASE + 0x28e) /* CAN4 transmitter control reg */ 00524 #define CAN4TXERR *(volatile unsigned char *)(IO_BASE + 0x28f) /* CAN4 transmit error counter */ 00525 #define CAN4IDAR0 *(volatile unsigned char *)(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */ 00526 #define CAN4IDAR1 *(volatile unsigned char *)(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */ 00527 #define CAN4IDAR2 *(volatile unsigned char *)(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */ 00528 #define CAN4IDAR3 *(volatile unsigned char *)(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */ 00529 #define CAN4IDMR0 *(volatile unsigned char *)(IO_BASE + 0x294) /* CAN4 id mask register 0 */ 00530 #define CAN4IDMR1 *(volatile unsigned char *)(IO_BASE + 0x295) /* CAN4 id mask register 1 */ 00531 #define CAN4IDMR2 *(volatile unsigned char *)(IO_BASE + 0x296) /* CAN4 id mask register 2 */ 00532 #define CAN4IDMR3 *(volatile unsigned char *)(IO_BASE + 0x297) /* CAN4 id mask register 3 */ 00533 #define CAN4IDAR4 *(volatile unsigned char *)(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */ 00534 #define CAN4IDAR5 *(volatile unsigned char *)(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */ 00535 #define CAN4IDAR6 *(volatile unsigned char *)(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */ 00536 #define CAN4IDAR7 *(volatile unsigned char *)(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */ 00537 #define CAN4IDMR4 *(volatile unsigned char *)(IO_BASE + 0x29c) /* CAN4 id mask register 4 */ 00538 #define CAN4IDMR5 *(volatile unsigned char *)(IO_BASE + 0x29d) /* CAN4 id mask register 5 */ 00539 #define CAN4IDMR6 *(volatile unsigned char *)(IO_BASE + 0x29e) /* CAN4 id mask register 6 */ 00540 #define CAN4IDMR7 *(volatile unsigned char *)(IO_BASE + 0x29f) /* CAN4 id mask register 7 */ 00541 #define CAN4RXFG *(volatile unsigned char *)(IO_BASE + 0x2a0) /* CAN4 receive buffer */ 00542 #define CAN4TXFG *(volatile unsigned char *)(IO_BASE + 0x2b0) /* CAN4 transmit buffer */ 00543 00544 00545 00546